Power analyzer of linear feedback shift register techniques using built in self test

Kannadhasan Suriyan, Nagarajan Ramalingam, Kanagaraj Venusamy, Sathish Sivaraman, Kiruthiga Balasubramaniyan, Manjunathan Alagarsamy


Wasteful patterns that don't lead to fault dropping squander a tone of energy in the linear-feedback shift register and circuit under examination in a random research region. Random switching actions in the CUT and scan pathways between applications with two consecutive vectors are another significant cause of energy loss. This study proposes a unique built-in self-test (BIST) technique for scan-based circuits that might help save energy. Only the available vectors are produced in a fixed series thanks to a mapping logic that alters the LFSR's state transitions. As a consequence, and without reducing fault coverage, the time it takes to execute trials has decreased. Experiments on circuits demonstrated that during random testing, the linear feedback shift register saves a significant amount of power.


BIST; CUT; LFSR; Power analysis; Verilog

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DOI: https://doi.org/10.11591/eei.v11i2.3331


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Bulletin of EEI Stats

Bulletin of Electrical Engineering and Informatics (BEEI)
ISSN: 2089-3191, e-ISSN: 2302-9285
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).