An improved ant colony optimization algorithm for wire optimization

Ho Joon Jim, Fazida Hanim Hashim

Abstract


Wire optimization has become one of the greatest challenges in today’s circuit design. This paper presents a method for wire optimization in circuit routing using an improved ant colony optimization with Steiner nodes (ACOSN) algorithm. Circuit delay and power dissipation are primarily affected by the length of the routed wire. Thus, the main goal of this proposed algorithm is to find the shortest route from one point to another using an algorithm that relies on the artificial behavior of ants. The algorithm is implemented in the JAVA programming language. The proposed ACOSN algorithm is compared with the conventional ant colony optimization (ACO) algorithm in terms of efficiency and routing performance when applied to three types of circuits: emitter-coupled logic, 741 output and a cascode amplifier. The performance of the proposed method is analyzed based on circuit information such as total wire routing, total number of nets, total wire reduction, terminals per net and total terminals. From the simulation analysis, it is shown that the proposed ACOSN algorithm gives the most benefit to complex circuits, where it successfully reduces the wire length by 21.52% for a cascode amplifier circuit, 14.49% for a 741 output circuit, and 10.43% for emitter-coupled logic circuit.



Keywords


Ant colony optimization; Circuit routing; Heuristic algorithm; Steiner nodes; Wire optimization

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DOI: https://doi.org/10.11591/eei.v9i5.2268

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