Simulation study of memristor aided logic (MAGIC) based on CMOS NOR gate

Wan Mohamad Izzat Wan Zain, Syed Abdul Mutalib Al Junid, Mohd Faizul Md Idros, Abdul Hadi Abdul Razak, Fairul Nazmie Osman, Abdul Karimi Halim, Muhammad Adib Haron

Abstract


Memristor is a non-volatile new technology memory where the data stored as a resistance which the performance is influenced by the stateful logic design. Therefore, this study is an attempt to investigate the performance of the MAGIC NOR Gate stateful logic design using LTSPICE and targeted to 2 bits memory application. The objective is to investigate the performance of memristor based stateful logic logic design and schematics for memory application. Furthermore, the study been carried out by implementing the MAGIC NOR gate stateful logic schematic, then simulate the design in order to see the effects of performance including the electrical parameters compared to the others. Evidently, the improvement of MAGIC NOR gate contributes in reducing the number of NOR gate and CMOS count. Besides, the MAGIC NOR gates takes parallel inputs topology and eliminate the threshold voltage compared to IMPLY logic. Nevertheless, larger numbers of memristor required to stable the output consistency in MAGIC NOR gate schematic.

 


Keywords


Logic gate; Memristor with CMOS; NOR gate

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DOI: https://doi.org/10.11591/eei.v9i5.2367

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