A cascade multi-level inverter topology with reduced switches and higher efficiency

Abstract

The use of multi-level inverter (MLI) technologies in high-power, medium-voltage energy regulation has been more popular in recent years. Despite the fact that the multilayer inverter has a lot of benefits, it has certain disadvantages in the layer of higher levels due to the enormous number of semiconductor switches that it employs in its construction. This may result in the inverter being of a huge size and costing a lot of money, as well as a significant rise in losses. As a result, the new MLI is suggested to minimize the number of switches in order to alleviate these challenges. This article describes a cascaded multilevel inverter with lower devices. The suggested cascaded multilevel inverter is intended for use in minimizing total harmonic distortion (THD), as shown in MATLAB/Simulink by the graph. Multilevel inverters benefit from the switching pattern of semiconductor switches, which may be used to improve their overall performance. This approach lowers the switching loss while simultaneously increasing the efficiency. In order to validate the suggested approach, simulations are carried out using the MATLAB/Simulink programming environment.