Memory faults using open and short defect models for nano technology applications

Abstract

As technology progresses from sub-micron to nanometer scales, memory-based systems are increasingly prone to faults. Consequently, developing robust methodologies to achieve defect-free embedded static random-access memory (SRAM) has become a critical challenge in modern very large scale integration (VLSI) design. Also, the increased integration of layout layers leads to form unknown defects. From the existing literature, observed that huge parametric variation is present whenever technology is changed. This is the key issue addressed in this paper, by representing an analysis on the impact of open and short defect models that uses parasitic extraction method while drawing various fault models. Possible open/short defects between the existing nodes are considered for the development of fault models using 45 nm, 32 nm, and 7 nm technologies. The total number of fault models of both kinds observed are 147. Also observed that besides to the existing faults, few undetectable faults are found named as undefined short faults (USF), undefined write after read fault (UWARF), and few faults with multiple faulty behavior.