Efficient Implementation of Mean, Variance and Skewness Statistic Formula for Image Processing Using FPGA Device

Aqwam Rosadi Kardian, Sunny Arief Sudiro, Sarifuddin Madenda


Processing statistic formula in image processing and accessing data from memory is easy in software, the other hand for hardware implementation is more dificult considering a lot of constraint. This article proposes an implementation of optimum mean, variance and skewness formula in FGPA Device. The proposed circuit design for all formulas only need three additions component (in three accumulators) and two divisions using two shift-right-registers, two subtractors, one adder and six multipliers. For 8x8 image size need 64 clock cycles to finish the mean, variance and skewness calculations, comparing other approach that need more than 1024 additions component without skewness calculation. Implementation into FPGA needs 68 slices of flip-flops and 121 of 4 input LUTs.


Counter and accumulator, FPGA, Mean, Skewness, Variance

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DOI: https://doi.org/10.11591/eei.v7i3.687


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